Ans. A typical instruction cycle can be split into many sub cycles like Fetch instruction, Decode instruction, Execute and Store. The instruction cycle and the corresponding sub cycles are performed for each instruction. These sub cycles for different instructions can thus be interleaved or in other words these sub cycles of many instructions can be carried out simultaneously, resulting in reduced overall execution time.This is called instruction pipelining.
The more are the stages in the pipeline, the more the throughput is of the CPU.
If the instruction processing is split into six phases, the pipelined CPU will have six different stages for the execution of the sub phases.
The six stages are as follows:
Fetch instruction (FI):
Decode instruction ((DI)
Calculate operand (CO):
Fetch operands (FO):
Execute Instruction (EI):
Write operand (WO):
Instructions are fetched from the memory into a temporary buffer before it gets executed.
The instruction is decoded by the CPU so that the necessary op codes and operands can be determined.
Based on the addressing scheme used, either operands are directly provided in the instruction or the effective address has to be calculated.
Once the address is calculated, the operands need to be fetched from the address that was calculated. This is done in this phase.
The instruction can now be executed.
Once the instruction is executed, the result from the execution needs to be stored or written back in the memory.