Questionbanks  DLDA 
A quick guide to Bh.QuestionbanksBrainheaters Questionbanks is the collection of handpicked set of questions which are mostly repeated, important and recommended. Learning this set of questions can easily help you top or even just clear the exams. Given below are Expected Questionbanks for semester.
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MODULE1 1. Convert Decimal number (Data) into binary, base4, octal, hexadecimal system. 2. A 7 bit even parity hamming code is received as 100010. Correct it for any errors & extract 4 bit data. 3. Convert (Data) to its equivalent sign magnitude form. (Data) 4. Construct Hamming code for BCD (Data). Use even parity. OR Design a logic circuitto convert BCD to Gray code. 5. Perform subtraction using 16’s complement. (Data) OR Perform subtraction using 2’s complement at for (Data) OR Find 8’s complement of following numbers. (Data) 6. Explain the term prime Implicant. 7. Convert (Data) into Excess3 code. OR Perform addition of (Data) 8. Explain ASCII code in brief. MODULE2 1. Express the equation in standard SOP form: (Given Data) OR Minimize the following standard POS expression using Kmap. (Given Data) OR Simplify the following equation using Kmap to obtain minimum SCOP equation & realize the minimum equation using two level NAND gates only (Given Data) 2. Reduce using Quine McCluskey method & realize the equation using only NAND gates.(Given Data) 3. Prove using boolean algebra: "NAND gate is universal gate". 4. Prove that “A positive logic and operation is equivalent to a negative logic OR operation”. 5. Prove ORAND configuration is equivalent to NORNOR configuration 6. Implement the following Boolean equation using NAND gates only. OR Simplify (B+A)(B+D)(A+C)(C+D). 7. Write the entity declaration in VHDL for NOR gate. 8. State and prove De Morgan's law MODULE3 1. What is Multiplexes Implement the following function using 4:1 multiplexer and few gates. (Given Data) OR Implement the following using 8:1 MUX. (Given Data) 2. Develop the truth table for 2bit binary multiplier & design it using a suitable decoder & additional gates. 3. Develop the truth table of 3 bit binary to gray code converter and design it by using 3:8 decoder with active low outputs & additional gates. 4. 2bit Magnitude comparator. 5. Implement the following functions using demultiplexer.(Given Data) OR Design 1:16 Demultiplexer using I:4 Demultiplexer. 6. Priority encoder. 7. Carry look ahead adder. MODULE4 1. Draw JK flipflop using SR flipflop & additional gates. Explain briefly the race around condition in JK flipflop 2. Design MOD7 synchronous upcounter. Show all the design steps. OR Design mod 12 asynchronous UP counter. 3. Draw a circuit diagram for MOD10 asynchronous binary up counter using masterslave JK flipflops. Show the output of each of the flipflop with respect to the clock applied, write the state transition table and explain the operation in brief. 4. What is shift register? Draw a 4bit universal shift register & explain PISO & SIPO operations. 5. Draw & explain the working of 4bit twisted ring counter with timing diagram. 6. List the applications of shift registers. 7. Explain Astable multivibrator. OR State table. 8. Draw the circuit for SR flip flop using two NOR gates and write the architecture body for the same using structural modeling. 9. ALU IC 74181 10. Sequence Generator 11. What is race around condition? How to overcome it? 12. Moore and Mealy machine. MODULE5 1. Write the entity declaration construct in VHDL for NOR gate. 2. Explain Data flow modelling and Behavioral modelling in VHDL 3. Explain the features of VHDL and its modeling. styles. MODULE6 1. Compare TTL & CMOs with respect to speed, power dissipation, fanin & fanout & also define these terms. 
