Questionbanks  DSD 
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MODULE1 1. Explain the following decimals in gray code form: (Given any Numerical) 2. Perform the following operation using 2’s complement. (Given any Numerical) 3. Convert (Given any Numerical) into decimal,binary and hexadecimal. MODULE2 1. State basic theorems of Boolean algebra. 2. Design a full adder using half adders and logic Gates. 3. State and prove the De Morgan's theorem. 4. Implement (Given any Numerical) using only NOR gates. 5. Compare TTL with CMOS logic families. 6. Design a full adder using 3:8 Decoder. 7. If (Given any Numerical) with its truth table and express F in SOP and POS form. 8. Prove that NAND and NOR Gates are universal Gates. 9. Design a 2 bit comparator and implement using logic gates. 10. Implement the given function using single 4:1 Multiplexer and few logic gates: (Given any Numerical) 11. Minimize the following expression using Mccluskey Technique (Given any Numerical) 12. Draw a neat circuit of BCD adder using IC 7483 and explain. 14. Implement the following Boolean function using 8:1 multiplexer. (Given any Numerical) 15. Using Boolean Algebra Prove the following: (Given any Numerical) MODULE3 1. Compare SRAM with DRAM. MODULE4 1. Compare Mealy and Moore machine. 2. Compare Combinational circuits with Sequential circuits. 3. Compare Synchronous counter with Asynchronous counter. 4. Explain Master slave JK Flip Flop. 5. Convert T flip flop to D flip flop. 6. What is a universal shift register? Explain its various modes of operation. 7. Convert JK FF to T FF and JK FF to D FF. 8. Explain the working of 3bit asynchronous counter with proper timing Diagram. 9. Design synchronous counter using D type flip flops for getting the following: Sequence: 0 → 3 → 1 → 5 → 6 → 0. Take care of lockout Condition. 10. What is shift register? Explain any one type of shift register.Give its Application. 11. What are Shift registers? How are they classified? Explain working of any one type of shift register. 12. Design a Mealy type sequence detector circuit to detect a sequence 1011 using D type flip flops. ( 13. Explain the Johnson's Counter. Design for initial state 0110. From initial state explain and draw all possible states. MODULE5 1. Draw the internal logic diagram of Programmable Logic Array (PLA). 2. Draw the internal logic diagram of Programmable Logic Array (PLA). 3. Explain CPLD and FPGA 4. Write a note on CPLDs. 5. Explain Full Adder circuit using PLA having three inputs,8 product terms and two outputs. MODULE6 1. VHDL Code for Full Subtractor. 2. Write a VHDL program to design a 3:8 Decoder. 3. Write the VHDL code for 3bit updown counter with negative edge triggered clock and active low Preset and Clear terminals. 
